Semiconductor lithography equipment is used to transfer circuit patterns onto a semiconductor chip.
By making further miniaturization possible at low cost, Canon’s nanoimprint lithography technology is about to trigger a revolution in semiconductor manufacturing.
2019/7/11 Featured Technology
The evolution of semiconductor chips correlates directly to the history of circuit miniaturization. The key to this miniaturization has been the shortening of light-source wavelengths and advances in lithography technologies. In the early 1990s, Canon introduced its i-line 365 nm wavelength (nm = nanometer, one billionth of a meter) steppers, making 350 nm resolution possible for a variety of imaging applications. In the late 2000s, new shorter-wavelength light sources were developed, leading to the creation of an argon fluoride (ArF) immersion lithography system capable of 38 nm-resolution patterning. At the time, it was believed that miniaturization had reached its technological limit.
As the industry looked for further breakthroughs, including extreme ultraviolet (EUV) lithography, Canon sought alternatives to shorter wavelengths, establishing a new approach to circuit miniaturization. That approach was nanoimprint lithography (NIL), which exceeds conventional lithographic limitations and does so at lower cost. Capable of achieving line widths of under 15 nm using a simple process that lowers manufacturing costs, NIL is poised to revolutionize the semiconductor industry.
While line widths have halved roughly every five years, progress has stalled since the late 2000s
Unlike conventional lithography technology that uses light to expose circuit patterns, nanoimprint lithography fabricates nanometer-scale patterns by transferring the nano-pattern mask (mold) onto the coated resin on the wafer surface to form circuits. Because the process involves no optical system, it enables the faithful reproduction of the mask’s minute circuit patterns on the surface of the wafer. However, because the circuit patterns are formed using direct transfer, the process requires nanometer-level control technologies for accurately positioning the mask and wafer, eliminating particle contaminants and other operations. Through the comprehensive development of hardware, software and materials technologies, along with environmental control technologies to keep microscopic particles in check, Canon successfully overcame these numerous obstacles.
One of the technologies Canon developed for nanoimprint lithography controls the amount and positioning of the resin that is applied to the wafer surface. This technology precisely controls how much and where the resin is applied to prevent it from being squeezed out when the mask is pressed into the resin, while also ensuring the formation of a resin layer with a uniform thickness. Likewise, when the mask is removed from the wafer, their relative positions must be optimally controlled to prevent the deformation of the convex circuit patterns formed in the resin.
With the aim of mass-producing nanoimprint lithography systems, Canon is collaborating with U.S.-based Canon Nanotechnologies, Inc. (CNT), which boasts some of the world’s most advanced and unique technologies for microfabrication devices in the field of nanoimprint lithography. In addition to lithography system control and measuring technologies achieved through Canon’s development of semiconductor lithography systems, Canon’s service and support know-how will be merged with CNT’s cutting-edge nanoimprint lithography technologies to break down the current barriers to miniaturization, once thought inviolable.
While photolithography has contributed to reducing the cost of semiconductor chips, further miniaturization required various workarounds that resulted in ever-larger and more expensive lithography systems. In contrast, nanoimprint lithography offers the simple approach of physically pressing patterns on a mask onto the resin. The simplified manufacturing process has the potential to significantly lower costs. Also, because this approach produces extremely sharp circuit patterns, it is expected to contribute to lower chip-defect rates.
There are two components to the jetting control technology used during the process to dispense resist to a wafer: technology to calculate the optimal application distribution when dispensing resist and technology to accurately dispense the resist according to the calculated application distribution.
Because the optimal resist application distribution differs depending on the concave patterns etched on the mask, Canon has developed a proprietary algorithm that assumes various cases. For example, when the mask is pressed against the resist, the algorithm calculates the behavior of the system as the resist is spread to the concave portions of the pattern as well as the necessary conditions for ensuring high-speed spreading. The resist placement intervals are widened in the direction of the gaps in the concave portions where resist can move easily, and more resist is placed where there are more concave portions. In this way, a resist application distribution is generated according to the orientation of concave portions of the pattern and the density (Fig.). In addition, to accurately dispense the resist according to the optimal application distribution, the status and behavior of the multiple nozzles used to dispense resist are individually managed, controlled, and adjusted. Canon applies measurement, control, and other technologies it has cultivated for its inkjet technology to achieve accurate application.
Fig. Circuit-Pattern CAD Information and the Generated Resist Droplet Pattern
Application that requires precise droplet control (10 seconds)
Unlike conventional projection-type lithography equipment, NIL mask directly contacts with the resist, so the equipment and the resist interact. Therefore, the resist material is an extremely important factor that has a major effect on imprinting performance.
Various types of performance are demanded of the resist material, including the filling speed for the concave patterns etched on the mask, the curing speed during UV light irradiation, the ability to retain shape against the release force that occurs when the mask is separated from the resist, and etching durability. As a result, developing this material takes an extremely long time.
In general, when the composition of a material is changed to improve one aspect of performance, this affects a different aspect of performance as well. When it comes to compositional design, two approaches are possible: designing an optimal composition that strikes a balance between many aspects of performance, or coming up with a new idea that resolves all the current issues in one fell swoop. Canon has improved wettability of the resist on a wafer wettability to dramatically improve the filling speed without affecting the separation force.
Because semiconductor chips are manufactured by stacking multiple pattern layers, it is necessary to achieve highly accurate alignment with patterns on lower layers. For NIL equipment, it is necessary to align transferred patterns that are tens of nm* in size with nm-level accuracy.
To achieve high-accuracy measurement of positional deviations, Canon has developed a system that makes it possible to measure the positional deviations between the mask and the wafer in real time (Fig. 1). By using optimal moiré patterns as well as proprietary optical technologies and control technologies developed in collaboration with Canon Nanotechnologies (CNT), NIL equipment can measure and correct for positional deviations between the mask and the wafer with a nanometer-level accuracy.
In addition to technology enabling high-accuracy measurement of positional-deviation information, matching technology enabling alignment with lower-layer patterns is also important. For its NIL equipment, Canon has developed a proprietary matching system that achieves alignment by using laser irradiation to thermally deform the wafer (Fig. 2). This system makes it possible to change the heat input pattern and freely deform the wafer by controlling an ultra-fine mirror group called a DMD. Instead of assuming that generated heat is a sort of disturbance that worsens the alignment precision as is conventionally thought, Canon has taken an innovative new approch to alignment (Fig. 3). By developing technologies suitable for NIL equipment based on its optical and control technologies, Canon has achieved nm-level alignment for imprinting as well.
Fig. 1: TTM Scope Enabling the Measurement of the Positional Deviations Between the Mask and Wafer in Real Time
Fig. 2: Proprietary Matching System
Fig. 3: Wafer Temperature and Shape After Deformation
Superimposing that accurately transfers circuit patterns (32 seconds)
In the semiconductor industry, particles (particulate foreign matter) are a cause of defective devices and have therefore long been a problem. For NIL, because the mask is pressed against resist on the wafer to form patterns, particle management is extremely important. If particles end up between the mask and the wafer when pressing them together, it can cause not only defective devices but destruction of the pattern on the mask itself.
Canon considered the eradication of particles an extremely high priority issue starting at the earliest stages of its NIL equipment development. To address this issue, Canon has developed various technologies to incorporate into its equipment. These include ultra-high performance filters that make it possible to eliminate particles and utilize design technology enabling the smooth flow of air into NIL equipment in spite of its complexity and many moving parts (Fig. 1). Canon also employs particle-elimination units to deal with particles that manage to get into the equipment and air curtains (Fig. 2) used to section off ultra-clean environments for the most important areas by dividing areas based on how clean they are.
Due to the development of these technologies, NIL has resulted in the achievement of some of the cleanest semiconductor manufacturing equipment in the world.
Fig. 1. Ultra-High-Performance Filter
Fig. 2. Air Curtain
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