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Exceeding the Limits of MiniaturizationExceeding the Limits of Miniaturization

Nanoimprint Lithography

Semiconductor lithography equipment is used to transfer circuit patterns onto the wafer. For its semiconductor lithography equipment, Canon is using nanoimprint lithography technology that achieves semiconductor-device miniaturization at a lower cost to innovate in the semiconductor industry.

2018/12/27Featured Technology

#Open innovation#Industrial equipment technologies#Patents#Mechanical engineering#Electrical engineering#Computer science#Physics#Chemistry#Semiconductors

Nanoimprint Lithography, the Ultimate Microfabrication Technology

The evolution of semiconductor chips is closely linked to the history of circuit-pattern miniaturization. In the past, the key to achieving miniaturization has been the development of shorter wavelength light sources to use for exposure and exposure technology to handle miniaturization. In the early 1990s, Canon introduced its i-line (365 nm wavelength; nm: nanometer = one billionth of a meter) lithography equipment and achieved a level of miniaturization making 350 nm patterns possible. Later, even shorter wavelength light sources were developed, culminating in the development of ArF immersion lithography equipment in the late 2000s, which achieved 38 nm patterns. It was said that the technological limit had been reached.
As various companies try to achieve breakthroughs in terms of EUV light sources, etc., Canon has opted for a different approach. Instead of trying to make light wavelengths shorter, the company is attempting to pave the way for additional miniaturization with a new technology that achieves miniaturization at a lower cost. This technology is called nanoimprint lithography (NIL), and it is expected to lead to innovations in the semiconductor industry because it makes it possible to inexpensively manufacture patterns at the 15 nm scale or smaller by using a simple process.

The History of Semiconductor Miniaturization

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While line widths have halved roughly every five years, progress has stalled since the late 2000s

How Canon's Nanoimprint Lithography Technology Works

Exposure technology has contributed to reducing the cost of semiconductor chips, but miniaturization requires various techniques, which has resulted in the required equipment becoming large and expensive. In contrast, nanoimprint technology uses a simple method to form patterns, which is to press a mask on which circuit patterns are etched against resist. This simpler manufacturing process is expected to lead to considerable cost reductions. In addition, because extremely sharp circuit patterns can be formed, the chip defect rate is also expected to decrease. Because nanoimprint technology does not require projection lens to form the patterns like existing lithography equipment does, there is no flare or aberration, which are imaging-performance limiters specific to optics. As a result, it is possible to form extremely high-resolution, clear patterns even at the ultra-fine level of tens of nanometers (Fig.).

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Jetting Control Technology for Imprint Resist

Visualizing Phenomena Invisible to the Naked Eye by Developing a Proprietary Algorithm

There are two components to the jetting control technology used during the process to dispense resist to a wafer: technology to calculate the optimal application distribution when dispensing resist and technology to accurately dispense the resist according to the calculated application distribution.
Because the optimal resist application distribution differs depending on the concave patterns etched on the mask, Canon has developed a proprietary algorithm that assumes various cases. For example, when the mask is pressed against the resist, the algorithm calculates the behavior of the system as the resist is spread to the concave portions of the pattern as well as the necessary conditions for ensuring high-speed spreading. The resist placement intervals are widened in the direction of the gaps in the concave portions where resist can move easily, and more resist is placed where there are more concave portions. In this way, a resist application distribution is generated according to the orientation of concave portions of the pattern and the density (Fig.). In addition, to accurately dispense the resist according to the optimal application distribution, the status and behavior of the multiple nozzles used to dispense resist are individually managed, controlled, and adjusted. Canon applies measurement, control, and other technologies it has cultivated for its inkjet technology to achieve accurate application.

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Fig. Circuit-Pattern CAD Information and the Generated Resist Droplet Pattern

Application that requires precise droplet control (10 seconds)

Optimal Resist Material Technology for NIL

Contributing to Improved NIL-Equipment Performance

Unlike conventional projection-type lithography equipment, NIL mask directly contacts with the resist, so the equipment and the resist interact. Therefore, the resist material is an extremely important factor that has a major effect on imprinting performance.
Various types of performance are demanded of the resist material, including the filling speed for the concave patterns etched on the mask, the curing speed during UV light irradiation, the ability to retain shape against the release force that occurs when the mask is separated from the resist, and etching durability. As a result, developing this material takes an extremely long time.
In general, when the composition of a material is changed to improve one aspect of performance, this affects a different aspect of performance as well. When it comes to compositional design, two approaches are possible: designing an optimal composition that strikes a balance between many aspects of performance, or coming up with a new idea that resolves all the current issues in one fell swoop. Canon has improved wettability of the resist on a wafer wettability to dramatically improve the filling speed without affecting the separation force.

Nanometer-Level Alignment Technology for Imprinting

Dramatically Improved Equipment Performance Based on Canon's Optical and Control Technology

Because semiconductor chips are manufactured by stacking multiple pattern layers, it is necessary to achieve highly accurate alignment with patterns on lower layers. For NIL equipment, it is necessary to align transferred patterns that are tens of nm* in size with nm-level accuracy.

  • * nm
    nanometer, one billionth of a meter

To achieve high-accuracy measurement of positional deviations, Canon has developed a system that makes it possible to measure the positional deviations between the mask and the wafer in real time (Fig. 1). By using optimal moiré patterns as well as proprietary optical technologies and control technologies developed in collaboration with Canon Nanotechnologies (CNT), NIL equipment can measure and correct for positional deviations between the mask and the wafer with a nanometer-level accuracy.

In addition to technology enabling high-accuracy measurement of positional-deviation information, matching technology enabling alignment with lower-layer patterns is also important. For its NIL equipment, Canon has developed a proprietary matching system that achieves alignment by using laser irradiation to thermally deform the wafer (Fig. 2). This system makes it possible to change the heat input pattern and freely deform the wafer by controlling an ultra-fine mirror group called a DMD. Instead of assuming that generated heat is a sort of disturbance that worsens the alignment precision as is conventionally thought, Canon has taken an innovative new approch to alignment (Fig. 3). By developing technologies suitable for NIL equipment based on its optical and control technologies, Canon has achieved nm-level alignment for imprinting as well.

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Fig. 1: TTM Scope Enabling the Measurement of the Positional Deviations Between the Mask and Wafer in Real Time

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Fig. 2: Proprietary Matching System

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Fig. 3: Wafer Temperature and Shape After Deformation

Superimposing that accurately transfers circuit patterns (32 seconds)

Particle Control Technology

Achieving Clean Semiconductor Manufacturing Equipment

In the semiconductor industry, particles (particulate foreign matter) are a cause of defective devices and have therefore long been a problem. For NIL, because the mask is pressed against resist on the wafer to form patterns, particle management is extremely important. If particles end up between the mask and the wafer when pressing them together, it can cause not only defective devices but destruction of the pattern on the mask itself.
Canon considered the eradication of particles an extremely high priority issue starting at the earliest stages of its NIL equipment development. To address this issue, Canon has developed various technologies to incorporate into its equipment. These include ultra-high performance filters that make it possible to eliminate particles and utilize design technology enabling the smooth flow of air into NIL equipment in spite of its complexity and many moving parts (Fig. 1). Canon also employs particle-elimination units to deal with particles that manage to get into the equipment and air curtains (Fig. 2) used to section off ultra-clean environments for the most important areas by dividing areas based on how clean they are.
Due to the development of these technologies, NIL has resulted in the achievement of some of the cleanest semiconductor manufacturing equipment in the world.

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Fig. 1. Ultra-High-Performance Filter

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Fig. 2. Air Curtain

Generating Synergies From Different Cultures

In the nanoimprint lithography field, Canon is collaborating with U.S.-based Canon Nanotechnologies (CNT), owner of some of the world's most advanced and unique technologies for microfabricated devices.
Canon's proprietary lithography-equipment control and measuring technologies as well as the company's service and support know-how are essential to the development of semiconductor lithography equipment. By merging these with CNT's cutting-edge nanoimprint lithography technologies, Canon aims to overcome current technological limits to break through the miniaturization barrier.

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